Training Memristors For Reliable Computation

The computation goals of the digital computing world has been segmented into different factions. The goals are no longer stemmed in a purely speed/performance standpoint but added requirements point to power awareness. This need for technological advancement has pushed researchers into a CMOS+X field whereby CMOS transistors are utilized with emerging device technology in a hybrid space to combine the best of both worlds. This dissertation focuses on a CMOS+Memristor approach to computation since memristors have been proposed for a large application space from digital memory and digital logic to neuromorphic and self-assembling circuits.
Specifically three application spaces are investigated. The first is a neuromorphic approach whereby spike-timing-dependent-plasticity (STDP) can be combined with memristors in order to withstand noise in circuits. The second application is memory; specifically we show a procedure to program and erase a memristor memory. The third approach is an attempt to bridge higher level learning to a memristor crossbar therefore paving the way to realizing self-configurable circuits. The approach or training methodology is compared to Q-Learning to re-emphasize that reliably using memristors may require not knowing the precise resistance of each device but instead working with relative magnitudes of one device to another.