MICL Seminar

Silicon Integration Choices in Sub-45nm Power Limited Microprocessors

Siva Narendra

Traditional scaling of microprocessors relies on performance improvement of general purpose computations. This is achieved through augmented architecture and circuit design complexities, apart from device technology scaling. The performance improvement from architectural and circuit complexities increase demands higher level of integration and die size growth. Scaling of device technology results in increased sub-threshold and tunneling leakage currents. This combination of device scaling and integration trend results in ever increasing power consumption which cannot be sustained in the long run. Implementation of special purpose power efficient applications in future microprocessors enables us to add functionality without significant power penalty. In this talk, I will first highlight the above mentioned scaling trends and the resulting power challenges. Next, I will present the benefits of special purpose computation to achieve better power efficiency by highlighting two communication applications – TCP/IP network processing and Ultra Wide Band wireless PHY layer implementation.
Siva Narendra received the Ph.D. degree in Electrical Engineering from Massachusetts Institute of Technology, Cambridge in 2002. He has been with Intel Microprocessor Research Labs since 1997, where his research areas include low voltage MOS analog and digital circuits and impact of MOS parameter variation on circuit design. He has authored or co-authored 31 papers and has 39 issued and 26 pending patents in these areas. Dr. Narendra is an Adjunct Faculty with the Department of Electrical and Computer Engineering, Oregon State University, Corvallis. He is an Associate Editor for the IEEE Transactions on VLSI systems and a member of the ISLPED, ISQED and ISSCC Student Design Contest Technical Program Committees.

Sponsored by

Micron and SSEL