Signal-Processing-Friven Integrated Circuits for Energy Constrained Microsystems

The exponential growth in IC technology has enabled low-cost and increasingly capable wireless sensor nodes which provide a promising way forward to realize the vision of a trillion connected sensors in the next decade. However there are still many design challenges ahead to make these sensor nodes small, low-cost, secure, reliable and energy efficient to name a few. Since the wireless nodes are expected to operate on a limited energy source or in some cases on harvested energy, the energy consumption of each building block is of prime importance to prolong the life of a sensor node. It has been found that in a generic sensor node, the radio communication when active has been one of the highest energy consuming modules on the sensor node. Thus, we have explored the signal processing techniques to come up with a low-power radio architecture for wireless communication and at the same time have looked into embedded machine learning to reduce the overall wireless network traffic resulting in an energy efficient network utilizing distributed intelligent sensing. Three prototype chips are presented. The first chip exploits compressed sensing to reduce receiver power for Ultra-Wide-Band (UWB) communication. The second prototype chip exploits the sensitivity vs. power trade-off for a Zigbee radio receiver and the time-varying channel characteristic to adapt the sampling frequency of the receiver while maintaining the desired system performance. The third chip is a hardware accelerator for arbitrary Bayesian network to make probabilistic inference which is being used for intelligent sensing.