Scalable Interconnect Architectures for Many-Core Systems

The ever-increasing demand for performance scaling has made multi-core (2-8 cores) chips prevalent in today's computing systems and foreshadows the shift toward many-core (10s-100s of cores) chips in the near future. Although the potential performance gains from
many-core systems remain appealing, the widespread adoption of these systems hinges on their ability to scale performance while simultaneously maintaining Quality-of-Service (QoS) and energy-efficiency constraints.

This work makes the case that the interconnect for these many-core systems has a significant impact on the aforementioned scalability issues. The impact of interconnects on many-core systems is illustrated in this work by observing that the degree of the interconnect has a significant effect on system scalability and demonstrating that the architecture of such high-radix, many-core systems are feasible designs. A Ï at crossbar interconnect, the Swizzle-Switch Network, is shown to be advantageous to traditional Network-on-Chip (NoC) for systems of up to 64 cores. This work also demonstrates how the optimized crossbar technology found in the Swizzle-Switch Network can be used to build high-radix NoC topologies that can support many-core architectures. Finally, the impact that 3D stacking technology has on many-core scalability is evaluated and shown to help crossbar and bus interconnects scale past their traditional limitations.