RRAM-Based In-Memory Computing Architecture Designs

   DNN applications usually lead to high computation costs and complexity. IMC methods can circumvent the von Neumann bottleneck and enable highly parallel computing, leading to high hardware efficiency and performance.

   To start, we present a reconfigurable RRAM-based IMC design that can accelerate general arithmetic and logic functions, which is specifically suitable for handling data-intensive tasks with very low power consumption.

   Next, we discuss DNN accelerator designs using an RRAM-based tiled IMC architecture. Popular models were mapped and tested. Effects of finite RRAM array size, device non-idealities, and ADC quantization effects were analyzed and addressed.

   Then we developed TAICHI architecture based on tiled RRAM crossbar arrays heterogeneously integrated with local and global digital components. It will allow efficient mapping of different models while maintaining high energy efficiency and throughput. The system is future-proof, as it can accommodate models larger than on-chip storage capability.

   To address the high ADC overhead and device variability problem, we proposed a hardware implementation of binary-weight SNNs (BSNNs). Binary activations allow readout, data routing, and neuron circuit design optimizations. Binary weights offer high tolerance to device variations. The proposed architecture can achieve high energy efficiency and accuracy for common SNN datasets with hardware and algorithm co-optimizations.

Chair: Professor Wei D. Lu