Dissertation Defense

Power-Efficient Neural Interface Circuits for Multi-Channel Deep-Brain Opto-Electrophysiology

Sungjin Oh
3316 EECS BuildingMap
Sungjin Oh Defense Photo

PASSCODE: 003754


A neural interface is an essential tool for monitoring brain activities. To observe and modulate the sophisticated neuronal ensembles, the neural interface circuit should be configured with a large number of channels that fulfill the strict specifications in noise, resolution, and bandwidth, but consume low power. Therefore, power-efficient circuit architectures are necessary to implement the high-performance large-scale neural interface. This dissertation focuses on neural recording/stimulation front-end circuit designs for power-efficient multi-channel deep-brain opto-electrophysiology interface.

   First work presents a high-channel-count opto-electrophysiology interface IC. Power- and area-efficient designs are employed to implement the largest scale optogenetic interface IC reported up to date. The miniature headstage using the fabricated interface IC achieves outstanding channel densities in size and weight. Second, an LFP-adaptive dynamic zoom-and-track recording front-end IC is presented. The zoom-and-track scheme, exploiting the 1/f spectral characteristics of the deep-brain signals, relaxes the speed requirement of the incremental ΔΣADC; thus, reduces its power consumption significantly. Finally, a slope-adaptive dynamic zoom-and-track recording front-end IC is presented. Through the improved zoom-and-track scheme, the front-end circuit records the tiny neural signals interfered by large and fast-varying transients, without degrading the resolution. Therefore, this work achieves the power-efficient neural recording without information loss due to the large interferences.


CHAIR: Professor Euisik Yoon