Neuromorphic Chip Design with a Scalable Architecture for Learning in Networks of Spiking Neurons
Add to Google Calendar
We present a scalable integrated circuit platform for networks of spiking neurons. The proposed platform incorporates (a) robust digital neuron circuits that exploit CMOS scaling; (b) novel transposable SRAM arrays that share learning circuits; and (c) crossbar fan-out for efficient on-chip inter-neuron communication. Through tight integration of memory (synapses) and computation (neurons), a highly configurable chip comprising 256 neurons and 64K binary synapses with on-chip learning based on spike-timing dependent plasticity is demonstrated in 45nm SOI-CMOS. Near-threshold, event-driven operation at 0.53V is demonstrated to maximize power efficiency for real-time pattern classification, recognition, and associative memory tasks. Future scalable systems built from the foundation provided by this work will open up possibilities for future brain-like computing systems.
Jae-sun Seo received the B.S. degree in electrical engineering from Seoul National University, Korea, in 2001, and the M.S. and Ph.D. degree in electrical engineering from the University of Michigan in 2006 and 2010, respectively. He spent graduate research internships at Intel circuit research lab in 2006 and Sun Microsystems VLSI research group in 2008, exploring new circuits for on-chip communication in microprocessors. In 2010, he joined IBM T. J. Watson Research Center, where he is presently a research staff member, working on energy-efficient integrated circuits for high-performance processors and cognitive computing chips. Mr. Seo was a recipient of Samsung Scholarship from 2004 to 2009, received a IBM outstanding technical achievement award in 2012, and serves on the technical program committee for ISLPED 2013.