Energy Efficient Hardware Design for Securing the Internet of Things
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The Internet of Things (IoT) is a rapidly growing field that holds potential to transform the everyday lives of people by placing tiny devices and sensors everywhere. The ubiquity and scale of IoT devices requires them to be extremely energy efficient. Given the physical exposure to malicious agents, security is a critical challenge within the constrained resources. This dissertation presents energy-efficient hardware designs for IoT security.
First, this dissertation presents a lightweight Advanced Encryption Standard (AES) accelerator design, using deep optimization of the datapath to achieve state-of-art area and energy efficiency. Second, the inflexibility and high Non-Recurring Engineering (NRE) costs of Application-Specific-Integrated-Circuits (ASICs) motivate a more flexible solution. This dissertation presents a reconfigurable cryptographic processor, which achieves performance and energy improvements for a wide range of security algorithms across public key / secret key cryptography and hash functions. The proposed design employs circuit techniques in-memory and near-memory computing and is more resilient to power analysis attack. Finally, an error resilient register circuit is designed to tolerate unpredictable variations in manufacturing process operating temperature and voltage of VLSI systems. When integrated into an ARM processor, this adaptive approach outperforms competing industrial techniques such as frequency binning and canary circuits in performance and energy.