Design Techniques for Scalable Fully Integrated CMOS Digital Beamforming Receivers
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Large-scale digital beamforming arrays offer several compelling advantages for emerging mm-wave wireless applications. Digital beamforming supports multiple simultaneous users without an SNR penalty and provides accurate beampatterns, fast steering, and a small chip area. Antenna size at mm-wave enables compact large-scale arrays, which provide increased SNR and narrowed, directed beampatterns. A tiled approach to scaling array size can minimize mm-wave routing losses and reduce die area and cost. This thesis examines circuit, module, and system design techniques for tiled digital beamforming arrays.
The first prototype introduces a single-tile 16-element CMOS digital beamformer that forms the foundation for a multi-chip array. This design integrates a compact mm-wave frontend with bandpass CTDSM ADCs and power- and area-efficient digital bit-stream processing. The chip is mounted on a custom substrate with a 4×4 array of patch antennas in a fully integrated mm-wave-to-digital beamforming module.
The second prototype scales the first work to a four-chip, 64-element module. Two circuit designs address crucial challenges in multi-chip scaling: a multi-chip digital PLL synchronizes the digital clock phase between chips, and a 13Gbps chiplet-to-chiplet interface, compatible with downstream digital processors, transfers up to four beam-space outputs between chips. A distributed partial beamforming scheme and a spiral module-level layout conserve chip I/O and distribute computational processing throughout the array. Four chips are mounted on a custom substrate with an 8×8 array of patch antennas, constructing a 64-element fully integrated digital beamforming module.
CO-CHAIRS: Professors Michael Flynn and David Wentzloff