Challenges and Opportunities for Mixed Signal Systems in Sub-100nm CMOS Technologies
The continued scaling of CMOS transistors provides significant challenges and opportunities for designers of mixed signal systems. We will review scaling trends and discuss its implications for incipient mixed signal systems. Using examples drawn from high- speed digital, low frequency as well as Radio frequency analog design applications, we will describe the impact of reducing voltages while simultaneously increasing leakage currents. We will also discuss, the space of realizable systems in the context of available device bandwidth and integration levels.
Krishnamurthy Soumyanath received his B.E. in Electronics and Communication Engineering from the Regional Engineering College, Tiruchirappalli in 1979, his M.S. in Electronics from the Indian Institute of Science, Bangalore in 1985 and his Ph.D. in Computer Science from the University of Nebraska at Lincoln in 1993. He was a member of the faculty at Tufts University in Medford, MA until 1995 where he served as the Director of the ARPA supported program in Mixed Signal IC design for the Department of Defense. Since 1996, he has been with Intel Corporation, where he is a principal engineer and currently leads the CMOS communications circuits effort for Intel's Corporate Technology Group. His previous responsibilities include leading several high-speed digital research projects for the Circuits Research laboratory. In 1998, he served as the Chair of the Design Sciences task force for the Semiconductor Research Corporation and currently serves on the Technical Program committee for ICCD. He has published over 15 papers in VLSI, and 6 patents issued. In addition to CMOS circuits of all kinds, his current research interests include classical Tamil poetry.