Successive Approximation and Time Interleaving for Sub-90nm CMOS ADCs

In the early days of MOS integrated circuits (way back in the 1970's),
getting any kind of accurate analog-to-digital converter (ADC) to work was
very challenging. Designers only had depletion-mode and enhancement-mode
NMOS transistors to work with; and, getting even modest analog voltage gain
was quite difficult. The successive approximation ADC, which does not require
an amplifier (just a comparator), took off as a dominant ADC architecture in those early
days of MOS. Then, as CMOS took hold in the 1980's, many other ADC architectures
took over and successive approximation became just one of many possible choices.

As CMOS process technology scales below gate lengths of 90nm, achieving
analog voltage gain is again becoming a major challenge. In part, the more three
dimensional nature of a very short channel MOSFET results in drain induced
barrier lowering that typically drops the maximum gain of a single transistor amplifier down
into the 5-10X range. Further, because the power supply voltages have dropped
down to 1V or below, adding cascode transistors to increase voltage gain is also difficult.
In this talk, the successive approximation ADC architecture will be reviewed. Two
very different 45nm CMOS ADC designs that were recently developed at Carnegie
Mellon will be described. The first ADC adopts digital error correction techniques to
increase the accuracy of the basic successive approximation ADC to over 11 bits.
The second ADC to be described develops strategies for achieving extremely high
sampling rates (over 2GS/s) using time interleaving of successive approximation ADCs.
The conclusion of this talk is that the characteristics of deeply scaled CMOS technologies
have caused a re-emergence of the popularity of successive approximation ADCs.

L. Richard Carley received an S.B. in 1976, an M.S. in 1978, and a Ph.D. in 1984, all
from the Massachusetts Institute of Technology. He joined Carnegie Mellon University
in Pittsburgh Pennsylvania in 1984, and in March 2001, he became the STMicroelectronics
Professor of Engineering at CMU. Dr. Carley's research interests include design, modeling
and analysis of hardware and algorithms related to data communications networks,
human/cyber networks, and data storage devices. The technologies he applies to these
systems include analog and RF integrated circuit design in deeply scaled CMOS technologies
and novel nano-electro-mechanical device design and fabrication. Dr. Carley has been granted
15 patents, authored or co-authored over 120 technical papers, and authored or co-authored
over 20 books and/or book chapters. He has won numerous awards including Best Technical
Paper Awards at both the 1987 and the 2002 Design Automation Conference (DAC).
In 1997, Dr. Carley co-founded the analog electronic design automation startup Neolinear
which was acquired by Cadence in 2004.