Solid-State and Nanotechnology
Quantum Tunneling Electronics for Ultra-Low Power Scaled CMOS
The dawn of tunnel diodes, commonly attributed to Leo Esaki in the late 1950's, predates much of the innovation and infrastructure investment into CMOS technology. But, the lack of a mass production process and inability to monolithically integrate these devices into complex circuits paved the way for the CMOS juggernaut seen today.
However, the unique negative differential resistance (NDR) systemic to all tunnel diodes provides a pathway to exploit new hybrid-CMOS circuit topologies with compact latches and reduced power consumption that could mitigate some of the bottlenecks perceived for scaled CMOS. A new paradigm of computing is possible, capitalizing upon transistor/tunnel diode integration if a viable Si-based tunnel diode could be developed. This talk will explore these opportunities.
By trading one materials science dilemma with another, studies of Si-based interband tunnel diodes were re-visited in the late 1990's, but via an epitaxial platform instead of the Esaki-era alloy process. The key hindrance to this approach is dopant diffusion and segregation that prevents degenerate doping across a narrow p-n junction. This team pursued the usage of Î&rquo;-doping and low temperature molecular beam epitaxy (LT-MBE) to suppress the dopant redistribution. If the growth and processing conditions are optimized, the Î&rquo;-doping layers can create quantum wells leading to a Si-based resonant interband tunneling diode (RITD) configuration.
This talk will provide a background on Si-based tunnel diode devices and circuits and summarize the results of Si-based RITD device optimization, their monolithic integration with Si-based transistors and present a range of circuit prototyping. Recent developments to technology transfer this technology from molecular beam epitaxy (MBE) to standard CMOS chemical vapor deposition (CVD) will be highlighted. The extension of NDR to ultra-low voltage memory will also be discussed.
Paul R. Berger is a Professor in Electrical & Computer Engineering at Ohio State University and Physics (by Courtesy). He is the Founder of the Nanoscale Patterning Laboratory. He received the B.S.E. in engineering physics, and the M.S.E. and Ph.D. (1990) in electrical engineering, respectively, all from the University of Michigan, Ann Arbor.
Currently, Dr. Berger is actively working on conjugated polymer-based optoelectronic and electronic devices; molecular electronics; Si/SiGe nanoelectronic devices and fabrication processes; Si-based resonant interband tunneling diodes and quantum functional circuitry; and semiconductor materials, fabrication and growth.
Formerly, he worked at Bell Laboratories, Murray Hill, NJ (1990-1992) and taught at the University of Delaware in Electrical and Computer Engineering (1992-2000). In 1999, Prof. Berger took a sabbatical leave while working first at the Max-Planck Institute for Polymer Research, Mainz, Germany while supported by Prof. Dr. Gerhard Wegner and then moved on to Cambridge Display Technology, Ltd., Cambridge, United Kingdom working under Dr. Jeremy Burroughes. In 2008, Prof. Berger spent an extended sabbatical leave at IMEC (Interuniversity Microelectronics Center) in Leuven, Belgium while appointed as a Visiting Professor in the Department of Metallurgy and Materials Engineering, Katholieke Universiteit Leuven, Belgium.
He has authored over 100 articles, 5 book sections and been issued 16 patents with 3 more pending. Some notable recognitions for Dr. Berger were an NSF CAREER Award, a DARPA ULTRA Sustained Excellence Award, a Lumley Research Award, and a Faculty Diversity Excellence Award. He has been on the Program and Advisory Committees of numerous conferences, including the IEDM, ISDRS meetings. He currently is the Chair of the Columbus IEEE EDS/LEOS Chapter and Faculty Advisor to both Ohio State IEEE Student Chapters. He is a Fellow and Distinguished Lecturer of IEEE and a Senior member of OSA.