WIMS Seminar

Out-of-Plane Integration Technique for Biomedical Microprobe Arrays

Arno AartsVisiting Graduate StudentMicro System Integration (IMEC) and University of Leuven, Belgium

Silicon micro fabricated probe arrays are used to analyze the brain at the cellular level. In chronic applications active probe arrays can be used to record or stimulate neurons in vivo. Multiplexers, amplifiers and filters can be integrated into the base of the micro fabricated probe array. Due to the in-plane two-dimensional fabrication process the base of the probe array increases significantly. The base of the probe array is located beyond the implanted part of the probe array and sticks out of the cortex. Probe arrays containing a tall base can get clamped between the brain and skull itself. This results in tissue damage or device failure. It is key the probe array can move along the macro movements of the cortex tending the array is floating on top of the brain.
Bringing the shafts of the probe array perpendicular to the base realizes a slim-base probe array allowing to float on the cortical surface while retaining the embedded electronics. A new type of micromachined interconnect has been developed to establish electrical connection using extreme planarization techniques. With this type of interconnect, MEMS structures of different dimensions and functionality can be electrically and mechanically connected perpendicular to a backbone. The assembly is done using a flip-chip bonder. Test structures have been made and assembled perpendicular to the substrate to perform a contact resistance measurement. Preliminary tests were carried out with the implantation of a probe array into the parietal cortex of a rat.

Arno Aarts is a graduate student at the Catholic University of Leuven, Belgium. Focusing on a novel interconnect technique for out-of-plane biomedical probe arrays at IMEC and contributing to the European NeuroProbes project (6th framework). As an undergraduate he studied electrical engineering at the University of Twente from 2002 through 2006 with a thesis on through wafer interconnect technology for wafer-level-packaging, performed at IMEC.

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