Multi-objective Placement Optimization For High-performance Nanoscale Integrated Circuits
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With aggressive scaling of semiconductor manufacturing technology in recent decades, the complexity of integrated circuits has increased rapidly In addition, under modern technology nodes, devices use narrower and more resistive wires, shifting the performance bottleneck from gate delay to interconnect delay. These trends confound existing design technologies for timing closure and require major improvements in physical design automation to maintain the current pace of innovations in chip architecture. Modern VLSI design flows require considerable effort and time in physical layout, where transistor locations affect nearly all downstream optimizations during timing closure.
We present new algorithms and methodologies for placement optimization subject to various constraints. In particular, we develop a standalone wirelength-driven global placement algorithm to drastically improve quality of standard-cell locations and decrease runtime. This algorithmic framework was recently adopted in industry and has been extended by several university groups. Our research demonstrates integration of routability analysis within placement optimization, which is becoming increasingly important at upcoming semiconductor technology nodes. To broaden the scope of placement optimization, we study theoretical aspects of our placement algorithms, and develop a variety of extensions. As one such extension, we present a placement framework that improves the handling of datapath designs.