High-Performance Asynchronous Systems: Analysis, Optimization, and Applications

Hardware designers are currently confronting formidable challenges in the areas of power management, timing variability, chip complexity and high-speed clock distribution. Asynchronous (i.e. clockless) design offers solutions to these pressing design challenges. In this talk, I will begin with a brief overview of the current state of asynchronous design. I will then describe my research contributions towards a new asynchronous CAD tool flow for producing optimized high-performance systems. This includes a fast analysis method for pipelined asynchronous systems, an optimization framework for producing high-performance pipelines, and low-overhead testing and design-for-test techniques for dynamic timing validation of asynchronous circuits. I will go on to describe two applications of high-performance pipelined asynchronous systems: a novel microarchitectural optimization for loop constructs and a low-power and scalable globally-asynchronous locally-synchronous (GALS) interconnect for shared-memory chip multiprocessors (CMPs). I will conclude the talk with a discussion of future directions for asynchronous design.
Gennette Gill is a postdoctoral research scientist at Columbia University, where she conducts research on asynchronous interconnection networks for parallel processors under Professor Steven Nowick. Dr. Gill earned her PhD from the University of North Carolina at Chapel Hill in 2010 with advisor Professor Montek Singh. During her time in graduate school, she was supported by a National Defense Science and Engineering Graduate Fellowship and a National Science Foundation Graduate Research Fellowship. She earned her BS in computer science from the University of Nebraska-Lincoln in 2002.