CMOS RF Roadmap

Stewart S. Taylor, PhD,
Intel

The RF performance of scaled CMOS exceeds application requirments below 10GHz. Leveraging this excess performance with circuit innovation and radio architecture will allow CMOS radios to be implemented for any standard in a small die size, and in a digital process. This will be accomplished by minimizing the number of on-chip inductors and the amount of analog baseband filtering. Shifting more of the burden to sigma-delta data converters and baseband digital signal processing will facilitate this. Even flicker noise, a big challenge for narrow-band applications, can be managed in this way. CMOS technology will enable multi-radio platforms whose cost and size is dominated by the packaging and RF front-end.

Stewart S. Taylor joined Intel in January 2003 as a Principal Design Engineer. His current research focus is on radio architecture and circuit design that leverages the strengths and compensates for the weaknesses of CMOS technology. He received a Ph.D. in electrical engineering from the University of California at Berkeley in 1978.

Before joining Intel, he was with Tektronix, TriQuint, and Maxim. He has developed high-speed analog, data converter, and wireless / RF integrated circuits. He has thirty-two issued patents, and fourteen pending.

Stewart served on the program committee of the International Solid-State Circuits Conference for ten years, chairing the Analog Subcommittee for four years. He was the conference Program Chair in 1999. He was an Associate Editor of the IEEE Journal of Solid-State Circuits, and the recipient of the IEEE Third Millennium Medal for Outstanding Achievements and Contributions from the Solid-State Circuits Society. Stewart has taught part-time at Portland State University, Oregon State University, and the Oregon Graduate Institute for twenty five years. He is a senior member of the IEEE.