Wireless Communication Circuits in Nanometer CMOS Technologies
Professor Jeyanandh Paramesh,
Carnegie Mellon University
This talk describes recent research into two critical front-end building blocks in receivers for upcoming wireless standards. Multiantenna systems that exploit spatial information in the signal have been recognized as a key to boosting data rates and enhancing signal quality in high-performance wireless systems. The first part of this talk describes a compact, power-efficient four-antenna receiver in 90nm CMOS for beam forming and spatial diversity applications.
Nanometer CMOS technologies have played a critical role in enabling the realization of both low-cost RF front-ends and powerful digital signal processing baseband blocks. However, the design of the ADC, which forms the interface block between these two domains, has become increasingly difficult because of falling supply voltages and low intrinsic gain associated with nanometer CMOS. The second part of this talk describes the design of wideband ??? ADCs in nanometer CMOS technologies and the application of digital processing schemes to correct performance degradation caused by analog circuit impairments.
Jeyanandh Paramesh received the B.Tech. degree from IIT, Madras, the M.S. degree from Oregon State University, and the Ph.D. from the University of Washington, all in EE. He has held product development positions at Analog Devices and Motorola and more recently worked as a graduate researcher in the Communication Technology Labs at Intel. Dr. Paramesh was a recipient of the Chevron Engineering Scholarship (1997), the Intel Foundation Doctoral Fellowship (2003–2004), and the Analog Devices Outstanding Student Designer Award (2005).