Wire line channels and equalization techniques for data transmission at speeds 10Gps and above

The talk will focus on wire line channels and equalization techniques for data transmission at speeds 10Gps and above. Two chips are described to illustrate the different approaches. The first chip employs an ADC-based analog-front-end integrated into a DSP-based transceiver, aiming for both serial 10Gbps KR-backplane and long-reach-multimode-fiber (LRM) applications. The second one is a 2×23 Gbps CMOS transmitter/receiver chipset for 40 Gbps DQPSK Optical Transmission. Also included in the talk are various wide-band techniques for high speed clock and data distribution.
Jun Cao received the B.S. degree in physics from Peking University, Beijing, in 1994, the MSEE from the University of Michigan, Ann Arbor, in 1996 and the Ph.D. degree in electrical engineering from the University of California, Irvine, in 2003. In 1999, he joined the NewPort Communications, Irvine, CA, where he was one of the leading designers for the world's first CMOS SONET OC-192 receiver and transmitter. Since 2000, he has been with Broadcom Corporation, working on high-speed transceivers and data converters. He is currently a senior design manager in the Analog and RF Microelectronics Group, focusing on the development of multi-gigabit Serdes for networking/wireless applications and transceivers/ADC/DAC for optical communications. He has published more than 25 journal/conference papers, fourteen of them on ISSCC/JSSCC. He currently has more than 50 issued or pending U.S. patents. Dr. Cao was also a guest lecturer in the Department of EECS of the University of California, Irvine.