Synthesis Problems for Reliable Clock Network Design

Clock is one of the most important design components to be carefully synthesized in the course of digital system design. Today, due to the diverse parameter variation in deep-submicron design as well as the demand of fast clock speed, robust and reliable clock design is highly requested. In this talk, a number of important synthesis problems of reliable clock network are introduced. Those include the clock polarity assignment problem, adjustable delay buffer (or post-silicon tunable buffer) insertion problem, clock mesh optimization problem, and pre-bond testability problem of 3D clock tree. For each problem, a brief definition of the problem will be introduced followed by recent approaches and solutions to the problem.
Prof. Taewhan Kim received the B.S. and M.S. degrees in CS from Seoul National University, and the Ph.D. degree in CS from the University of Illinois at Urbana-Champaign. After graduation, he was working for Lattice Semiconductor and Synopsys for six years, specializing in design automation tool development. Currently, he is a professor with the EE department in Seoul National University. His research area is the computer-aided design of ICs, covering from the high-level synthesis to physical design, currently focusing on power, noise, reliability, and 3-D IC design issues. Prof. Kim is serving on the editor-in-chief of the International Journal of Computing Science and Engineering.