Straintronics: A Leap towards Ultimate Energy Efficiency of Magnetic Random Access Memory and Logic
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Aggressive scaling of CMOS technologies in the past decade has left circuit engineers with a plethora of design challenges. As the feature size in CMOS scales below 22 nm, static power dissipation due to multiple sources of leakage (weak inversion current, DIBL, GIDL, gate tunneling, etc.) becomes significantly large in digital circuits. The supply voltage, on the other hand, does not scale down equally. Therefore, the shorter channel length along with a high supply voltage leads to high leakage power dissipations. Integrated systems, therefore, are facing an increasing leakage to active power ratio. Another obstacle, which is mainly a concern for high speed applications, is the increasing energy density, which requires complicated cooling schemes and packaging. Further, battery technologies are not growing as fast as CMOS technology, leaving large portable systems with a few microwatts of power to live on. The above obstacles call for novel solutions to enable the industry to push the integration density as prophesized by Moore's law. Alternative technologies need to be combined with CMOS in order to overcome the shortcomings of CMOS chips.
This talk discusses one of the aforementioned prominent technologies, called magnetic random access memory (MRAM). While MRAM has been under research and development for decades, it has been only in recent years that advances in the technology made it competitive with ubiquitous CMOS memories, owing to MRAM's conventionally high switching energy. Beyond introducing MRAM, this talk covers an emerging write method, called straintronics, aimed at revolutionizing the energy efficiency of MRAM by proposing a piezoelectric-based switching method, potentially saving more than four orders of magnitude of switching energy compared to the most recent commercial MRAMs.