Robust Circuit Design for Low-Voltage VLSI
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Voltage scaling is an effective way to reduce the overall power consumption, but the
major challenges in low voltage operations include performance degradation and reliability issues
due to PVT variations. This dissertation discusses three key circuit components that are critical in
Level converters must be a reliable interface between two voltage domains, but the reduced
on/off-current ratio makes it extremely difficult to achieve robust conversions at low voltages.
Two static designs are proposed: LC2 adopts a novel pulsed-operation and modulates its pull-up
strength depending on its state. A 3-sigma robustness is guaranteed using a current margin plot;
SLC inherently reduces the contention by diode-insertion. Improvements in performance, power,
and robustness are measured from 130nm CMOS test chips.
SRAM is a major bottleneck in voltage-scaling due to its inherent ratioed-bitcell design. The
proposed 7T SRAM alleviates the area overhead incurred by 8T bitcells and provides robust
operation down to 0.32V in 180nm CMOS test chips with 3.35fW/bit leakage. Auto-Shut-Off
provides a 6.8x READ energy reduction, and its innate Quasi-Static READ has been
demonstrated which shows a much improved READ error rate. A use of PMOS Pass-Gate
improves the half-select robustness by directly modulating the device strength through bitline
Clocked sequential elements, flip-flops in short, are ubiquitous in today's digital systems. The
proposed S2CFF is static, single-phase, contention-free, and has the same number of devices as in
TGFF. It shows a 40% power reduction as well as robust low-voltage operations in fabricated
45nm SOI test chips. Its simple hold-time path and the 3.4x improvement in 3-sigma hold-time
is presented. A new on-chip flip-flop testing harness is also proposed, and measured
hold-time variations of flip-flops are presented.