Rethinking Embedded Memory for High Performance Microprocessors
With the advent of multi-core and multi-threaded microprocessors, the demand for high speed and high density embedded memory has dramatically increased. Compounding these trends with scaling challenges faced by traditional SRAM caches creates a pressing research area ripe with opportunity. While the motivation for such research is provided by the computer architecture community, a combined response by the circuits and technology communities is required to provide viable memory solutions. Research in this area will need to focus on methods to enable further SRAM scaling, beat SRAM scaling in terms of density and performance, and facilitate communication to logic cores by increasing memory bandwidth.
Leland Chang received the B. S., M. S., and Ph.D. degrees in electrical engineering and computer sciences from the University of California, Berkeley, where his doctoral work focused on the FinFET and related thin-body device structures. He joined the IBM T. J. Watson Research Center in 2003, where he is now Manager of Design and Technology Solutions. His current research focuses on interactions between technology and circuit design with a particular emphasis on variability solutions for low voltage SRAM.