Reining in the Functional Verification of Complex Processor Designs With Automation, Prioritization, and Approximation

Our quest for faster and efficient computing devices has led us to processor designs with enormous complexity. The process of ascertaining the correctness of these designs, known as functional verification, today takes up a lion's share of the time and cost spent on processor design projects. Its share is only expected to grow in the future. Yet, functional verification is only a best-effort process that cannot completely guarantee the correctness of a design, often resulting in defective products that may have devastating consequences.

We believe that functional verification is unable to cope with increasing design complexity because it is structured and practiced with an expectation of completeness. In this dissertation, we introduce the automation, prioritization, and approximation (APA) approach that serves as a lens through which we evaluate multiple aspects of the functional verification process while embracing incompleteness. We recognize that we cannot perform functional verification today without consciously prioritizing certain design aspects, verification tasks, and engineer efforts. We believe that automation, which builds upon strategic prioritization, is the key to improving functional verification efficiency. Furthermore, we explore reasonable approximations that trade modest losses in the fidelity of the activity that we automate for far more significant gains in its efficiency.

This dissertation presents our applications of the APA approach to develop solutions that facilitate efficient usage of powerful functional verification platforms, reduce the time and effort spent on verification planning, automate the tedious process of locating design errors, and enable new capabilities for detecting design errors.