Process and frequency scaling implications on high-frequency microprocessor CAD

Over the past decade, Intel has demonstrated that increasing the clock frequency is the most consistent way of improving general-purpose microprocessor performance. In this talk, after examining the assumptions that made this frequency scaling possible we will look at the challenges that the process and the high-frequency microprocessor roadmap poses to designers and CAD researchers. The latter part of the talk will focus on specific CAD challenges in timing verification and interconnect-driven design.

Noel Menezes manages the timing analysis and design research group in the Strategic CAD Department of Intel Labs. Researchers in his group work on timing analysis models and algorithms, high-frequency interconnect modeling, interconnect design, high-capacity CAD data infrastructures, and asynchronous design. Noel has worked on clock tree synthesis, timing models, and interconnect optimization with his work applied to the design of PowerPC and Pentium 4 microprocessors. Noel holds MS and PhD degrees from the University of Texas at Austin and a BE degree from Maharaja Sayajirao University, India.