Principled Secure Processor Design

Abstract

Arguably the foremost problem in Secure Computer Architecture is that processor microarchitecture leaks more privacy than is captured by explicit abstractions such as the ISA. This discrepancy matters, enabling devastating attacks capable of leaking critical, to potentially all, program data.

This talk will advocate for principled defenses that provide a basis for higher levels in the stack to reason about what leakage is possible at the hardware level. The talk will be broken into two parts. First, I will describe a hardware mechanism that transparently, and efficiently, enforces non-interference with respect to speculatively accessed data (blocking attacks such as Spectre). Second, I will describe a new HW/SW abstraction that provides a complete specification for what can leak at the ISA level. Along the way, I will detail subtle ways that modern hardware can leak, and abstractions through which we can think about information leakage on modern processors, taking inspiration from the applied cryptography and programming language communities.

Biography

Chris Fletcher is an Assistant Professor in Computer Science at the University of Illinois at Urbana-Champaign.  He has broad interests ranging from Computer Architecture to Security to High-Performance Computing (ranging from theory to practice).  These and related works have been awarded with election to the DARPA ISAT study group, the George M. Sprowls Award for Outstanding Ph.D. Thesis in Computer Science at MIT, multiple best paper awards and best paper honorable mentions, and were listed as one of ten “World Changing Ideas” designations by Scientific American.  He leads an Intel ISRA center studying processor security.