Part 1–A 4GS/s 4bit Flash ADC in 0.18µm CMOS
Sunghyun Park, Graduate Student, Univ. of Michigan
ABSTRACT: (Sunghyun Park) A 4GS/s, non-interleaved, 4b flash ADC in 0.18 µm CMOS is presented. A comparator with a 32 µm by 32 µm on-chip inductor extends sampling rate without extra power consumption. DAC trimming and comparator redundancy reduce DNL and INL to less than 0.15LSB and 0.24LSB respectively. The measured ENOB is 3.84b and 3.48b at 3GS/s and 4GS/s respectively. The ADC achieves a BER less than 10^-11.
BIO: Sunghyun Park received a bachelor degree from Seoul National University, South Korea in 1998, a master degree from University of Michigan, Ann Arbor, MI in 2003, and is currently pursuing his Ph.D. degree at the same school, all in electrical engineering. He interned at Intel’s Communication Technology Laboratory in 2004 and 2005 working on high speed data conversion circuits for UWB applications. At Intel, he successfully designed and characterized a 3.5GS/s 5 bit ADC prototype. He is a recipient of the Korean IT National Scholarship in 2001 and Intel Ph.D. fellowship in 2004.