Low-power Volatile and Non- volatile Memory Design
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With technology scaling, memory cell size get significantly minimized. However, Vmin of 6T SRAM didn't scale well in advanced technology. As a result, memory dominates power consumption in advanced computing systems like machine-learning accelerator and mm- scale sensor node system which has growing need for large amount of low-power memories. In this dissertation, several circuit and system solutions are proposed to reduce power consumption of different memory cells for different applications. The first topic is a 4+2T SRAM cell that uses the N-well as a write wordline, decoupling read/write paths with 15% area saving than 8T SRAM. Decoupled differential read paths significantly improve read noise margin, achieving 0.25V Vmin and enabling reliable multi-word activation for in- memory-computing and BCAM/TCAM applications. Next I will talk about another decoupled 5T SRAM cell with 7.2% area saving than 6T SRAM while achieving improved read margin. 4Mb 5T SRAM is applied to a face-recognition machine-learning accelerator. The second topic is a 1Mb sub-100µW embedded NOR flash for battery-powered miniature sensor-node system. Multiple low-power circuit techniques are applied into the high-voltage generation and delivery system and a margin-doubled cross-sampling current sense amplifier is proposed. Measurements in a 90nm embedded flash technology show 30— and 22— lower program and erase energy, respectively compared with a standard flash macro. The last topic is a low-power STT-MRAM in 28nm technology. A single-cap based offset-cancelled sense amplifier is proposed to improve sensing margin and in-situ self-termination write method is used to save write power.