Leveraging Sub-Threshold Digital Circuits to Minimize System-Level Power
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Extending the traditional operating range of digital CMOS circuits into the sub-threshold region provides new levels of ultra-low-power (ULP) consumption that enable a variety of emerging energy-constrained applications. Demonstrations of sub-threshold logic, memory, and processors have confirmed that sub-threshold operation can minimize energy consumption for digital logic. This talk explores taking the next step with sub-threshold circuits by placing them into a variety of system contexts. Taking the emerging class of body area sensor networks (BASNs) as an example, we examine how to leverage the strengths of sub-threshold digital circuits in a full ULP system. Specifically, we demonstrate a mixed signal IC for wireless electrocardiogram (ECG) monitoring. We also describe the application of sub-threshold techniques in traditionally high-performance contexts. As an example, we show how sub-threshold analysis can help minimize standby leakage reduction in a high-performance SRAM using a closed-loop feedback approach managed by a sub-threshold controller.
Benton Highsmith Calhoun received his B.S. degree in electrical engineering from the University of Virginia, Charlottesville, VA, in 2000. He received the M.S. degree and Ph.D. degree in electrical engineering from the Massachusetts Institute of Technology, Cambridge, MA, in 2002 and 2006, respectively. In January 2006, he joined the faculty at the University of Virginia as an Assistant Professor in the Electrical and Computer Engineering Department. His research interests include low-power digital circuit design, sub-threshold digital circuits, SRAM design for end-of-the-roadmap silicon, variation-tolerant circuit design methodologies, and low-energy electronics for medical applications. Dr. Calhoun is a co-author of Sub-Threshold Design for Ultra-Low-Power Systems (Springer, 2006).