Interconnect and Memory Design for Intelligent Mobile System
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Technology scaling has driven the transistor to a smaller area, higher performance and lower power consuming which leads us into the mobile and edge computing era. However, the benefits of technology scaling are diminishing today, as the wire delay and energy scales far behind that of the logics, which makes communication more expensive than computation. Moreover, emerging data centric algorithms like deep learning have a growing demand on SRAM capacity and bandwidth. High access energy and huge leakage of the large on-chip SRAM have become the main limiter of realizing an energy efficient low power smart sensor platform.
We will present several architecture and circuit solutions to enable intelligent mobile systems, including voltage scalable interconnect scheme, Compute-In-Memory (CIM), low power memory system from edge deep learning processor, and ultra-low leakage memory design for low power smart image signal processor.
We first propose a reconfigurable self-timed regenerator based global interconnect scheme to achieve higher performance and energy-efficiency in wide voltage range. Secondly, we introduce a hybrid in-/near-memory Compute SRAM with a wide range of flexible bit-width operations, implemented in a small IoT processor. Thirdly, we present the low power memory design for a deep learning processor with 270KB custom SRAM and Non-Uniform Memory Access architecture. Finally, we are exploring ultra-low leakage SRAM design for motion-triggered low power smart imager sensor system.
Chair: Professor Dennis Sylvester