FinFETs: A Designers Perspective

FinFETs: A Designers Perspective

We have recently reached the scaling limit of planar MOSFET devices. New process technologies (14-22nm) use 3D FinFET devices that have different DC and AC properties than standard planar devices. It is not all good! In this talk we will summarize the properties of FinFETs and describe how custom digital design is affected. Case studies will also be presented in order to explore some of the benefits and drawbacks of porting a design to a FinFET process.
Duke Xanthopoulos received his BS, MS and PhD from the Massachusetts Institute of Technology in 1992, 1995 and 1999 respectively. From 1999-2001 he was a design engineer with the Alpha microprocessor group (Compaq) where he designed and implemented the Alpha EV7 clocking system. Since 2001 he is with Cavium in the position of Distinguished Engineer . Among his responsibilities are high speed I/O design, power and signal integrity and new process technology adoption. He has been a member of the ISSCC program committee from 2001 to 2009. He has edited and co-authored "Clocking in Modern VLSI Systems", Springer 2009 and has multiple publications and patents.