Systems Seminar - CSE
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Modern processor architectures are complex machines due to decades’ worth of performance optimizations. This complexity can lead to subtle performance issues at the microarchitectural level that are very difficult to diagnose. Fortunately, modern processors also contain a rich set of performance monitoring facilities that enable introspection of many aspects of program execution. My research goal is to build automatic systems that can diagnose and repair performance issues in running programs, relieving programmers of the burden of performance tuning.
I’ll discuss our work on a series of hardware-software systems for C/C++ and Java that use performance counters to diagnose false sharing bugs in multicore programs, and then perform automatic online repair of these bugs to improve performance through careful consideration of the memory consistency model. These repair techniques are able to achieve much of the benefit of hand-written expert fixes, but require no programmer intervention. In ongoing work we are applying the feedback-driven processor methodology to the problem of front-end stalls in the datacenter. I’ll also discuss related efforts to improve performance and correctness via static and dynamic analysis of GPU programs and via deterministic execution systems.
Joseph Devietti is an Assistant Professor in the Department of Computer & Information Science at the University of Pennsylvania. His research focuses on making parallel computers easier to program, leveraging techniques across the computing stack, including computer architecture, compilers, runtime systems and programming languages. He was awarded an Intel Early Career Faculty Honor in 2013, and the Radhia Cousot Young Researcher Best Paper Award at SAS 2018. He earned his PhD in Computer Science & Engineering from the University of Washington in 2012.