Energy-Efficient Circuit Designs for Miniaturized Internet of Things and Wireless Neural Recording

Internet of Things (IoT) have become omnipresent over various territories including healthcare, smart building, agriculture, and environmental and industrial monitoring. Today, IoT are getting miniaturized, but at the same time, they are becoming more intelligent along with the explosive growth of machine learning. Not only do IoT sense and collect data and communicate, but they also edge-compute and extract useful information within the small form factor. A main challenge of such miniaturized and intelligent IoT is to operate continuously for a long lifetime within its low battery capacity. Energy efficiency of circuits and systems is key to addressing this challenge. This dissertation presents two different energy-efficient circuit designs: an ultra-low power gate-leakage-based timer for wireless sensor nodes (WSNs) for the IoT and an energy efficient all analog machine learning accelerator for IoT edge computing.

Wireless neural interface is another area that demands miniaturized and energy-efficient circuits and systems for accurate and safe long-term monitoring of brain activity. Historically, implantable systems have used wires for data communication and power, increasing risks of tissue damage. Therefore, it has been a long-standing goal to distribute sub-mm-scale true floating and wireless implants throughout the brain and to record single-neuron-level activities. This dissertation presents two generations of sub-µW and sub-mm wireless neural recording IC for motor prediction with near-infrared (NIR) power and data telemetry.

Chair:  Professor Dennis Sylvester