Efficient Retiming Algorithms for Wire Pipelining in System-on-Chip
With the rapid increase of both operating frequencies and chip sizes, many global wires in a System-on-Chip require multiple clock periods to propagate signals even after interconnect optimizations are applied. Wire pipelining, a technique of inserting flip-flops over wires, is therefore necessary to fulfill these requirements.
To maintain the functional correctness, we propose to employ the retiming technique to relocate flip-flops for wire pipelining. We will present efficient algorithms for this retiming problem to minimize the clock period.
Hai Zhou is an assistant professor in Electrical and Computer Engineering at Northwestern University. He got his Ph.D. degree in Computer Sciences from the University of Texas at Austin in 1999, and his B.S. and M.S. degrees in Computer Science and Technology from Tsinghua University in Beijing, China in 1992 and 1994, respectively. Before joining the faculty of Northwestern University, he was with the Advanced Technology Group at Synopsys, Inc. His research interests include VLSI computer-aided design, algorithm design, and formal methods. He has published more than 50 technical papers in prestigious journals and conferences in these areas. He was a recipient of a CAREER Award from the National Science Foundation in 2003, and served on the technical program committees of ACM International Symposium on Physical Design and IEEE International Conference on Computer-Aided Design.