Electrical and Computer Engineering

WIMS Seminar

Driving Down the Cost of MEMS Production Thru Wafer Level Test

Don Feuerstein
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National Sales and Marketing Manager
SUSS MicroTec, Inc.
Test Systems Division
Waterbury Center, VT

ABSTRACT:
This seminar will discuss the use of wafer level test as a means of driving down the cost of MEMS production. Because failed devices that are tested after final packaging incur substantial costs wasting not only money but R & D, process utilization and foundry time, creative solutions which allow testing while still in wafer form can save as much as 80% of the cost of MEMS production incurred during the packaging process. The largest single factor available to device manufacturers to cut costs is wafer level test. Unique test applications and equipment designed to bring device testing to wafer level ensures that the devices in the packaging line are known good die (KGD). Figure 1 (sorry, it is unavailable on line) shows that testing at the earlier stages of design and development when yields are typically lower results in cost savings that may exceed 15%.

BIO:
Don Feuerstein has been involved in the Semiconductor industry for over 10 years. SUSS MicroTec hired him to head up their North American Sales and Marketing efforts approximately 2 years ago. He is a leading contributor to furthering MEMS test technology within SUSS and the industry.

Don is a published author. He performed his under graduate work at North Eastern University, MA and earned his MBA at the University of New Haven, CT.

Sponsored by

WIMS ERC Seminar Series