Dissertation Defense

Design of Digital FMCW Chirp Synthesizer PLLs Using Continuous-Time Delta-Sigma Time-to-Digital Converters

Daniel Weyer


Automotive radar applications have spurred the development of frequency-modulated continuous-wave (FMCW) radar. The radar performance depends on high-quality signal sources for chirp generation, requiring fast-settling and low-phase-noise chirp synthesizers. Fractional-N phase locked loops (PLLs) are an effective tool to generate FMCW waveforms, and advances in CMOS technology have enabled high-performance single-chip CMOS synthesizers for FMCW radar. Digital synthesizer PLLs offer greater flexibility and area efficiency than their analog counterparts, but their close-in phase noise suffers from the limited resolution of conventional time-to-digital converters (TDCs).

This work presents digital FMCW chirp synthesizer PLLs based on noise-shaping TDCs that leverage state-of-the-art modulator techniques. First, we describe an 18-to-22GHz chirp synthesizer with a noise-shaping TDC that combines a conventional phase detector with a third-order modulator. Second, we introduce a noise-shaping TDC based on a continuous-time bandpass modulator. The bandpass TDC samples a sinusoidal PLL reference and relies on digital down-conversion. Using this TDC, we design a 36-to-38GHz digital chirp synthesizer PLL. A 40nm CMOS prototype achieves a measured close-in phase noise of -85dBc/Hz at a 100kHz offset for wide loop bandwidths >1MHz. It effectively generates fast (500MHz/55s) and precise (824kHzrms frequency error) triangular chirps for FMCW radar applications.

Sponsored by

Professor Michael Flynn