Compilation for SPM-based Manycore Architectures

Ever increasing requirements for power-efficiency are dramatically changing the way we compute. Multicores are a direct result of our need to improve power-efficiency, beyond what single-cores can deliver. However, as we continue to scale the number of cores, scaling the memory architecture is a major challenge. Cache coherency protocols do not scale well, and caches continue to be the major power hog in a processor. A scalable memory alternative is Scratch Pad Memory (SPM) based manycore architecture, in which each core has a local memory (or SPM), and the core can only access the SPM.
There is no hardware support for memory management and coherency, and therefore both must be taken care of, explicitly in the software. IBM Cell, which powers the Sony PS3 is an excellent example of such an architecture. The main promise of SPM-based manycores is that, if no management and coherency is needed in the application, then the execution is extremely power- efficient. However, the main challenge in the success of these architectures is the difficulty of programming "“ programmer needs to explicitly manage data and it's communication. To shield the programmer from this complexity, we have developed a compiler solution for automatic data management in SPM based manycore architectures. In this talk, I will summarize our efforts towards that, and will also give snapshots of some of our other research topics that might be of interest.
Prof. Aviral Shrivastava is Associate Professor in the School of Computing Informatics and Decision Systems Engineering at the Arizona State University, where he has established and heads the Compiler Microarchitecture Labs (CML) (http://aviral.lab.asu.edu/). He received his Ph.D. and Masters in Information and Computer Science from University of California, Irvine, and bachelors in Computer Science and Engineering from Indian Institute of Technology, Delhi. He is the recipient of 2011 NSF CAREER Award, and 2012 Outstanding Junior Researcher in CSE at ASU. His research focuses in three important directions, 1. Manycore architectures and compilers, 2. Programmable accelerators and compilers, and 3. Quantitative Resilience. His research is funded by DOE, NSF and several industries including Intel, Nvidia, Microsoft, Raytheon Missile Systems, Samsung etc. He serves on organizing and program committees of several premier embedded system conferences, including ISLPED, CODES+ISSS, CASES and LCTES, and NSF and DOE review panels.