CMOS mm-Wave Digital Beamformer Receiver with Parallelized Continuous-Time Band-Pass Delta-Sigma ADCs

Large-scale beamforming is an essential technology for emerging wireless communication systems. Digital beamforming offers superior beam-pattern accuracy, inherent flexibility, fast steering, and the ability to generate multiple, simultaneous beams without duplicating the element circuitry. However, element-ADC sets the performance bottleneck in a digital beamformer, sensitive mm-wave and analog signal lines are susceptible to local crosstalk, and the enormous raw data demands high-throughput digital processing.

In this thesis, 1) we introduce the concept of parallelized ADC with multi-phase sampling technique to improve ADC linearity, SNDR and provide inherent FIR filtering; 2) we present a prototype 16-element 1GHz IF digital beamformer with parallel element sub-ADC arrays confirming measured accurate beam-patterns. The measured 77dB SFDR proves the harmonic suppression from the multi-phase sampling; 3) we present a 16-element fully integrated 28GHz digital beamformer with an LTCC substrate incorporating a 4×4 patch antenna array. The inductor-less frontend and sub-ADC arrays enable compact mm-wave-to-digital conversion. The high 1GHz IF sampling facilitates single-phase LO distribution and digital I/Q mixing. Optimum bump and RX slice placement shorten both LO and signal routing; 4) we introduce a frequency-interleaving technique to expand the element ADC BW. The prototype 28nm CMOS chip achieves measured SNDR/SFDR of 37dB/44dB at 300MHz BW and 1.5GHz input frequency while consuming only 38mW, and 5) we discuss the advantages and challenges of a tiled beamforming system to support even more elements.

Chair: Professor Michael P. Flynn