Challenges in the Assembly of Microsystem Packages
5050 List Drive, Colorado Springs, CO 80919
Microsystems typically require a custom package and custom assembly process due to the unique requirements of each application. The assembly of a microsystem package usually involves a combination of materials and unit processes that are adapted from the IC industry as well as materials and unit processes that are unique to the microsystem application. In this paper, the author will review some of these assembly processes as they apply to specific microsystem devices. Special emphasis will be placed on microsystem package partitioning including the tradeoffs of packaging at the system, component and wafer level. The practical aspects of wafer dicing, die attach, wirebonding, flip chip as well as encapsulation and sealing processes will then be discussed. The talk will conclude with a discussion of the issues related to package assembly process integration for inertial, optical, RF and biofluidic applications.
Leland “Chip” Spangler, Ph.D. has more than 20 years of experience in the design, fabrication, packaging, assembly and reliability of microsystems and ICs. He received his BSE, MSE and Ph.D. all from The University of Michigan in 1982, 1984 and 1988 respectively, where he made contributions in the area of transistor design, and micromachining processes including wafer bonding as applied to sensors and circuits. He worked at Ford Electronics Division from 1989 to 1999 where he managed an engineering group responsible for pressure sensors, micromachined fuel injectors, and airbag and other accelerometers. Many of these devices passed automotive qualification requirements and subsequently reached high volume production. Dr. Spangler is the author of over 20 technical papers and has seven patents. He is currently the Director of Engineering at Aspen Technologies a semiconductor packaging foundry in Colorado Springs.