MICL Seminar

Challenges and Opportunities in High-Speed and Low-Power SRAM Design for Multi-Ghz Microprocessors

Kevin Zhange

High-performance microprocessors require ever larger and faster on-die SRAM to meet performance requirements. As the technology scaling drives the feature size of transistor below 100nm, it has become increasingly difficult to maintain the conventional scaling trend in SRAM density and performance while meeting power requirements. In this talk, many key challenges facing today’s SRAM design, ranging from SRAM cell design, array architecture, and power management are addressed in details from the perspectives of both technology and design. Innovative technology and design solutions, including cell stability enhancement, leakage reduction, and dynamic power-down and multi-VCC switching are presented.
Dr. Kevin Zhang is a senior principal engineer and design manager with Portland Technology Development at Intel. He leads the design and process vehicle development for Intel's future logic technologies. In this role, he is responsible for development of advanced memory technologies for both CPU and communications products at Intel. He is currently serving ISSCC technical program committee.

Sponsored by

Micron Technology Foundation