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EECS 523: Digital Integrated Technology

Integration density and performance of digital integrated circuits have undergone an astounding revo­lution in the last several decades. For both logic IC’s and memories, integration complexity and density has doubled every ~2 years, inline with Gordon Moore’s famed “law.” Although innovative circuit and system design can account for some of the accompanying performance increases, technology has been the main driving force. This course will examine the process technol­ogy that has enabled the digital revolution and investigate new technologies aimed at sustaining the current rate of progress in digital integrated circuits. The goal is to achieve a working knowledge of the driving and limiting factors of the design techniques employed, and of likely future trends.

Lab: There is no lab associated with this course.

Team project: Team of two or more students will be formed. The team is expected to do the device or/and process simulations using Silvaco or Cadence simulator. All selected topics will be related to digital IC technology.

Textbook: Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices, 2nd edition, Cambridge, 2009

Syllabus / class outline:

  1. Introduction
  2. Long channel MOSFETs
  3. Nano-scale CMOS process technology
  4. Short-channel MOSFETs
  5. CMOS device design and performance factors
  6. MOSFET scaling and technological solutions
  7. SOI field-effect transistors
  8. Fin-FETs structures, electrical characteristics, and process technology
  9. Nano-sheets FETs in a gate-all-around (GAAFET) configuration
  10. Nanowire FETs
  11. Process parameter variability and electrical reliabilities of MOSFETs
  12. Application of MOSFETs into digital circuits